2014: Ph.D., Graduate Institute of Electronics Engineering, National Taiwan University
2006: M.S., Department of Computer Science and Information Engineering, National Chung Cheng University
2002: B.S., Department of Computer Science and Information Engineering, National Chiao Tung University
Assistant Professor, Department of Electrical Engineering, National Cheng Kung University (2016/08 - present)
Lead Application Engineer, Cadence Design Systems, Inc. (2015/5 - 2016/7)
Senior Engineer, MediaTek Inc. (2014/5 - 2015/1)
Assistant Engineer, Industrial Technology Research Institute (2002/7 - 2003/9)
Formal Verification of Safety/Security Critical Systems
Y.-R. Chen, J.-J. Yeh, P.-A. Hsiung, and S.-J. Chen, “Accelerating Coverage Estimation through Partial Model Checking,” IEEE Transactions on Computers, Computer 63(7): pp. 1613-1625, 2014.
C.-S. Lin, P.-A. Hsiung, S.-W. Lin, Y.-R. Chen, C.-H. Lu, S.-Y. Tong, W.-T. Su, W. C. Chu, C.-H. Shih, N.-L. Hsueh, C.-H. Chang, and C.-S. Koong, "VERTAF/Multi-Core: A SysML-based Application Framework for Multi-Core Embedded Software Development," Journal of the Chinese Institute of Engineers, Vol. 32, No. 7, pp. 985-991, November 2009 (SCI).
P.-A.Hsiung, S.-W.Lin, Y.-R.Chen, C.-H.Huang, and W. C. Chu, "Modeling and Verification of Real-Time Embedded Systems with Urgency," Journal of Systems and Software (JSS) (SCI), Volume 82, No. 10, pp. 1627-1641, Elsevier Inc., October 2009.
P.-A. Hsiung, Y.-R. Chen and Y.-H. Lin, "Model Checking Safety-Critical Systems using Safecharts," IEEE Transactions on Computers (SCI), Vol. 56, No. 5, pp. 692-705, May 2007.
Y.-R. Chen and P.-A. Hsiung, "Automatic Failure Analysis using Safecharts," International Journal of Software Engineering and Knowledge Engineering (IJSEKE) (SCI), Vol. 17, No. 1, pp. 57-78, World Scientific Publishing, Singapore, February 2007.
Y.-R. Chen, S.-J. Chen, P.-A. Hsiung, I-H. Chou, “Unified Security and Safety Risk Assessment - A Case Study on Nuclear Power Plant,” TSA 2014: 22-28
Y.-R. Chen, Z.-R. Wong, P.-A. Hsiung, S.-J. Chen and M.-H. Tsai, “Backward Probing Deadlock Detection for Networks-on-chip,” International Symposium on Networks-on-Chip (NOCS), April 2013.
H.-L. Chao, Y.-R. Chen, S.-Y. Tong, P.-A. Hsiung, S.-J. Chen, “Congestion-aware scheduling for NoC-based reconfigurable systems,” Design, Automation & Test in Europe Conference & Exhibition (DATE), March 2012.
Y.-R. Chen , W.-T. Su, P.-A. Hsiung, Y.-C. Lan, Y.-H. Hu, and S.-J. Chen, "Formal Modeling and Verification of Network-on-Chip," Proceedings of the International Conference on Green Circuits and Systems, 2010.
Y.-R. Chen, T.-Y. Chen, P.-A. Hsiung, S.-J. Chen and Y.-H. Hu, "Compositional Automata Reduction with Non-critical Path Slicing," The 2009 International Conference on Foundations of Computer Science, pp. 133-138, CSREA Press, July 2009.
P.-A. Hsiung, C.-S. Lin, S.-W. Lin, Y.-R. Chen, C.-H. Lu, S.-Y. Tong, W.-T. Su, C. Shih, C.-S. Koong, N.-L. Hsueh, C.-H. Chang, William C. Chu, "VERTAF/Multi-Core: A SysML- based Application Framework for Multi-Core Embedded Software Development," Proceedings of the International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP), LNCS, Springer Verlag, June 2009.
P.-A. Hsiung, S.-W. Lin, Y.-R. Chen, N.-L. Hsueh, C.-H. Chang, C.-H. Shih, C.-S. Koong, C.-S. Lin, C.-H. Lu, S.-Y. Tong, W.-T. Su, and W. C. Chu, "Model-Driven Development of Multi-Core Embedded Software," Proceedings of the 2nd International Workshop on Multicore Software Engineering (IWMSE), May 2009.
Y.-R. Chen, P.-A. Hsiung, and S.-J. Chen, "Modeling and Automatic Failure Analysis of Safety-Critical Systems using Extended Safecharts," Proceedings of the International Conference on Computer Safety, Reliability and Security (SAFECOMP, Nuremberg, Germany), Lecture Notes in Computer Science (LNCS), Springer Verlag, September 2007.
P.-A. Hsiung , S.-W. Lin, Y.-R. Chen, C.-H. Huang, J.-J. Yeh, H.-Y. Sun, C.-S. Lin, and H.-W. Liao, "Model Checking Timed Systems with Urgencies," Proceedings of the 4th International Symposium on Automated Technology for Verification and Analysis (ATVA, Beijing, China), LNCS Vol. 4218, pp. 67-81, Springer-Verlag, October 2006.
S.-W. Lin, P.-A. Hsiung , C.-H. Huang, and Y.-R. Chen, "Model Checking Prioritized Timed Automata," Proceedings of the 3rd International Symposium on Automated Technology for Verification and Analysis (ATVA, Taipei, Taiwan), LNCS Vol. 3707, pp. 370-384, Springer Verlag, October 2005.
Ebook Editor: P.-A. Hsiung , Y.-H. Lin, and Y.-R. Chen, "Safecharts Model Checking for the Verification of Safety-Critical Systems," in Verification, Validation and Testing in Software Engineering , editors Aristides Dasso, Ana Funes, IDEA Group, Inc., USA, ISBN: 1-59140-851-2, 2007.
Invited Reviewer of IEEE Transactions on Computers
Invited Reviewer of International Symposium on Automated Technology for Verification and Analysis